Child Pages

• NHX5424_2_V01_400
• NHX5424_0_V01_400

Contents

• NHX5424 Specifications
  • IPQ5424
  • Key features
    • Wi-Fi subsystem:
    • Networking subsystem:
    • CPU: Quad-core ARM Cortex-A55 at 1.8 GHz
    • Memory:
    • Coexistence: PTA slave
    • Audio:
    • Security:
    • Package: 14.5 mm × 14.5 mm MSP480
  • Networking subsystem
  • Security
• IPQ5404
• Product Image

NHX5424 Specifications

IPQ5424

Key features

Wi-Fi subsystem:

• The Wi-Fi subsystem supports IEEE802.11be
• One integrated Wi-Fi MAC/BB operates in 2.4 GHz (4x4/40)
• Flexible Wi-Fi 7 radio configurations via 4x PCIe interfaces

Networking subsystem:

• 3x USXGMII/SGMII+
• MDIO configuration port to external PHY

CPU: Quad-core ARM Cortex-A55 at 1.8 GHz

Memory:

• JEDEC standard DDR3L/DDR4 DRAM
• Up to 8 GB for DDR4

Coexistence: PTA slave

Audio:

• Supports I2 S/TDM, PCM

Security:

• Trust Management Engine
• Inline security engine
• TrustZone

Package: 14.5 mm × 14.5 mm MSP480

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Networking subsystem

The IPQ5424 integrates three SerDes interfaces, each capable of speeds up to 10.3125 Gbps. These interfaces are part of a network processing subsystem that accelerates various packet processing operations, including parsing, WAN tunnel processing, classification, routing, switching, metering, editing, statistics collection, queuing, scheduling, and traffic shaping.

The network subsystem of the IPQ5424 can process 45 million packets per second and support an aggregate throughput rate of 30 Gbps, making it highly suitable for managing demanding workloads related to packet classification, packet forwarding, and complex traffic management in Wi-Fi 7 systems.

IPQ5424 integrates an inline security engine that supports AES 128/256, SHA1-96/128/256/512, and 3DES, and provides up to 2 Gbps throughput.

• Three SerDes interfaces for external Ethernet PHYs. Each SerDes interface supports USXGMII single port, 10GBase-R (SFP+, XFI), SGMII+ (3.125G), or SGMII (1.25G) mode.

• Packet Processing

  • Wirespeed WAN tunnel support

    • PPPoE, GRE, VxLAN, Q-inQ, NAT66

  • IP address management and translation

    • MAP-T, MAP-E, DS-Lite, NAPT

  • Packet Processing Engine (PPE) for standard L2-L4 routing/bridging of IPv4 and IPv6 packets

    • Flexible VLAN assignment and translation on ingress, including filtering, double tag, single tag,untag, priority tag
    • Classification based on L2/L3/L4 and User Defined fields; actions like policing, QoS Marking, en-queue, forwarding, and so forth
    • Flow based routing/bridging/NAT; IPv4 unicast routing and NAT, IPv6 unicast routing, PPPoE, IPMC bridging
    • MAC table for Bridge learning and aging, Station Movement control, L2 multicast, Spanning tree, Link aggregation
    • Egress Queues
      • 256 unicast and 44 multicast queues
      • PCP, DSCP, Flow, Classifier based Priority
      • Classifier based policer with two rate, three color meter, marker
      • Ingress scheduling, shaping
      • WRED lite with color aware dynamic, and static threshold
      • 2-level Scheduler, 3-level Shaper with CIR, EIR rate control (HTB lite)

  • Up to 64k flows between PPE and software-based fast path

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Security

• Datapath security engine

  • Look-aside acceleration supported
  • Up to 2 Gbps
  • AES 128, 256
  • SHA 1-96, 128, 256, 512
  • 3DES 1-96, MD5-96
  • CCM and GCM operation

• Trust Management Engine for SoC Root of Trust

• Crypto services

  • ARM TrustZone
    • Qualcomm Trusted Execution Environment (QTEE)

IPQ5404

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Product Image